1. Field of the Invention
This invention relates to a semiconductor memory device in which a plurality of memory cells are connected in series to constitute a memory cell unit.
2. Description of Related Art
A memory cell in an EEPROM has usually a MISFET structure which is formed of a semiconductor substrate with a charge storing layer and a control gate stacked thereabove. This memory cell stores data in a non-volatile manner, as defined by a threshold state in which charges are injected into the charge storing layer and another threshold state in which the charges have been released. The charge injecting/releasing is done by a tunneling current trough a tunnel insulating film between the substrate channel and the charge-storing layer. In various EEPROMs, a so-called NAND-type EEPROM, in which a plurality of memory cells are connected in series to constitute a NAND cell unit, may be formed with a high density because it is formed with select transistors less than a NOR-type EEPROM.
Data erase of the NAND-type EEPROM is usually performed by a block, and data write is by a page (for example, refer to Published and Unexamined Japanese Patent Application No. 2000-76882).
Data read is performed by: applying a read voltage to a control gate of a selected memory cell for judging threshold thereof; simultaneously applying a pass voltage to control gates of the remaining unselected memory cells which is higher than the read voltage and turns on the unselected memory cells without regard to cell data thereof; and detecting a “read current” flows through the NAND cell unit. However, even if selected memory cell's data are the same, these read currents are different from each other in accordance with the data states of the unselected memory cells and the position of the respective selected memory cells in the NAND cell unit. Further, since data read is based on detecting the charge amount flowing through the memory cells, there is a problem that the memory cell's threshold voltage appears to be varied.
It will be explained in detail referring to drawings that the read current appears to be different in accordance with the data states of the unselected memory cells and the selected cell's position. FIGS. 18A and 18B show two data read bias conditions different from each other with respect to a NAND cell unit NU constituted by sixteen memory cells connected in series. One end of the NAND cell unit NU is coupled to a data transfer line (hereinafter, referred to as a bit line) BL via a select transistor S1, and the other to a reference potential line (hereinafter, referred to as a common source line) SL disposed common to the memory cell array via another select transistor S2. Control gates of the memory cells are connected to different data control lines (hereinafter, referred to as word lines) WL, respectively, and gates of the select transistors S1 and S2 are connected to select gate lines SSL and GSL, respectively, for selecting a block.
Although only one NAND cell unit NU is shown in FIGS. 18A and 18B, a plurality of NAND cell units are arranged in the bit line direction and in the word line direction to constitute a memory cell array. A sense amplifier/data latch is coupled to the bit line BL. In case of a flash memory, an assemblage of NAND cell units arranged in the direction of word lines is defined as a block which serves as a unit of data erase. Note that a low threshold state obtained by releasing electrons of the charge storing layer is referred to as a data “1”, and a high threshold state obtained by injecting electrons into the charge storing layer as a data “0”, in the explanations described bellow.
FIGS. 18A and 18B show voltage relationships at a read time when a memory cell M0 nearest to the bit line BL is selected in the memory cells M0 to M15. As shown in FIGS. 18A and 18B, the source line SL is set at ground potential GND; the bit line BL is applied with a positive voltage VBL, for example, about 1V; the selected word line WL0 is applied with a read voltage Vr for judging data; the remaining unselected word lines WL1–WL15 are applied with a pass voltage Vread which is necessary to turn on cells without regard to these cells' data; and select gate lines SSL and GSL are applied with the pass voltage Vread.
FIG. 20 shows an example of cell data threshold voltage distributions in case of binary data storing. The upper limit of “0” data threshold voltage distribution, Vthw, is, for example, about 2V; the upper limit of “1” data threshold voltage distribution (i.e., erase state), Vthe, is, for example, about −1V. Therefore, a voltage selected in a range of 4V to 5V is used as the pass voltage Vread; and for example, 0V is selected as the read voltage Vr. FIG. 20 shows a threshold voltage distribution of the select transistors S1 and S2, which is lower than the upper limit Vthw of the write threshold voltage. Therefore, apply the pass voltage Vread to the select gate lines, and the select transistors S1 and S2 become conductive with a conductance value larger than those of memory cells.
FIG. 18A shows a case where data of the selected memory cell M0 is “1”; and the entire unselected memory cells M1–M15 are also storing data “1”. In contrast to this, in case of FIG. 18B, data of the selected memory cell M0 is “1”; and the entire unselected memory cells M0–M15 are storing data “0”. In these cases, the read currents ID1 and ID2 flowing through the respective NAND cell units are satisfied with a relationship of: ID1>ID2. The reason of this is in a fact that on-resistances between sources and drains of the respective unselected cells in the case of FIG. 18B are higher than those in the case of FIG. 18A.
FIGS. 19A and 19B show voltage relationships at a read time when a memory cell M15 nearest to the common source line SL is selected in the memory cells M0 to M15. FIG. 19A shows a case where the entire memory cells store data “1”. In contrast to this, in case of FIG. 19B, data of the selected memory cell M15 is “1”; and the entire unselected memory cells M0–M14 are stored with data “0”. Although, in these cases, memory cells M0–M14 operate in an active region (i.e., linear operation region) when the bit line voltage VBL is lower than Vread-Vthw, series resistance thereof in case of FIG. 19B becomes larger than that in case of FIG. 19A. Further, since the selected memory cell M15 operates in a linear operation region, the source-drain voltage is small. Therefore, the read currents ID3 and ID4 in case of FIGS. 19A and 19B are satisfied with a relationship of: ID3>ID4.
Considering a substrate bias effect for the respective memory cells, the threshold voltage of the memory cell M0 nearest to the bit line BL, a substrate bias applied to which is higher than that applied to the memory cell M15 nearest to the common source line SL, becomes higher than that of the memory cell M15. Therefore, ID2 is smaller than ID4, while ID1 is smaller than ID3.
So far, it has been explained that the read current of the NAND cell unit varies in accordance with the write data states of the NAND cell unit. This means that a data threshold voltage of a memory cell becomes different between before and after data writes into other memory cells. Explaining in detail, the above-described threshold variation will occur in case of proceeding erase, read and write sequences shown in, for example, FIG. 21 or FIG. 22.
In FIG. 21, firstly, the entire memory cells M0–M15 in the NAND cell unit are erased at a time into a “1” data state (step SE1). Then at step SE2, read the memory cell M0 under the bias condition shown in FIG. 18A. In detail, the cell data is judged as “0” or “1” based on a constant judging current Ith. Alternatively, another read scheme may be used in such a manner that precharging the bit line BL to VBL to let it be floating; and then sensing bit line voltage with a sense amplifier. Further, write “0” data into memory cells from M1 to M15, and cause threshold voltages thereof to be higher (step SE3). Next, at step SE4, read the memory cell M0 under the bias condition shown in FIG. 18B so as to judge whether the data is “0” or “1” based on the judging current Ith.
With this proceeding, in spite of the memory cell M0 is in the same erase state at steps SE2 and SE4, the read currents ID1 and ID2 are different from each other as described with FIGS. 18A and 18B, and this may lead to a situation that the read current ID2 at the step SE4 is less than the judging current Ith; and the read current ID1 at the step SE2 is greater than the judging current Ith. Explaining in other words, “1” data threshold voltage at step SE4 appears to be higher in the positive direction than that at step SE2 in spite of that data read is performed with the same judging current. That is, as shown in FIG. 20 by a dotted line and a solid line, it is generated a situation that “1” data shows two threshold distributions different from each other in appearance.
In FIG. 22, firstly, the entire memory cells M0–M15 in the NAND cell unit are erased at a time into a “1” data state (step SE1). Then at step SE2′, read the memory cell M15 under the bias condition shown in FIG. 19A. In detail, the cell data is judged as “0” or “1” based on a constant judging current Ith. Further, write “0” data into memory cells from M0 to M14, and cause threshold voltages thereof to be higher (step SE3′). Next, at step SE4′, read the memory cell M15 under the bias condition shown in FIG. 19B so as to judge whether the data is “0” or “1” based on the judging current Ith.
With this proceeding, in spite of the memory cell M15 is in the same erase state at steps SE2′ and SE4′, the read currents ID3 and ID4 are different from each other as described with FIGS. 19A and 19B, and this may lead to a situation that the read current ID4 at the step SE4′ is less than the judging current Ith; and the read current ID3 at the step SE2′ is greater than the judging current Ith. Explaining in other words, “1” data threshold voltage at step SE4′ appears to be higher in the positive direction than that at step SE2′ in spite of that data read is performed with the same judging current. That is, as shown in FIG. 20 by a dotted line and a solid line, it is generated a situation that “1” data has different threshold voltage distributions from each other in appearance.
On the other hand, if the read current of a logical data varies in accordance with a selected memory cell' position and data states of unselected memory cells, it becomes difficult to shorten a read time and reduce electro-magnetic noises due to the read current. This is because that the maximum read time is determined by a condition as the read current of the selected cell becomes minimum, and the maximum electromagnetic noise is determined by a condition as the read current of the selected cell becomes maximum.
Further, as the read current of the selected cell becomes larger, the common source line SL is more boosted in potential, and this leads to a trouble that “0” data write is not sufficiently done in case write and verify-read are repeated (for example, refer to Published and Unexamined Japanese Patent Application No. 11-260076). In addition, the larger the read current, the larger the maximum drain current which flows into the bit line, and this brings wiring resistance increase and reliability deterioration due to electro-migration based on current stress, and transistor threshold variation and leakage current increase due to heat up.
Further, as the judging threshold voltage of “1” data becomes higher, the voltage gap between the lower limit of “0” data threshold voltage distribution (i.e., Vthw2 in FIG. 20) and the upper limit of “1” data threshold voltage distribution (i.e., Vthe in FIG. 20) becomes less. This leads to increasing the probability of erroneous read such as to read out “1” data as “0” data. To prevent such the erroneous read, it may be required to, for example, to bring the “0” data threshold voltage distribution to a higher voltage range. However, this leads to another problem.
The data retention property is so influenced by the self electric field due to the stored charge that the retention of “0” data with a higher threshold voltage distribution is inferior to that of “1” data with a lower threshold voltage distribution. Therefore, if the “0” data threshold voltage distribution is brought to a too high voltage range, it becomes difficult to secure a sufficient data retention property.
In addition, unselected memory cells in the NAND cell unit are applied with a voltage higher than the upper limit of “0” data threshold distribution at a data read time, thereby brought in a weak write mode. Therefore, repeating the data read operation, the threshold voltage(s) of the erase state cell(s) in the unselected memory cells is boosted due to negative charge injection into the charge storing layer(s). This causes data disturbance, erroneous read and the like.
There have already been provided by us some schemes of reducing the read stress on the unselected memory cells due to that the read current varies in accordance with data states of the unselected memory cells and the selected cell's position (refer to Published and Unexamined Japanese Patent Application No. 2002-358792). According to one scheme, considering the drain conductance of the selected memory cell, the pass voltage applied to unselected memory cells is exchanged in accordance with the position of a selected memory cell in a NAND cell unit. Alternatively, another scheme is to use different two pass voltages such as one is applied to unselected memory cells located on the drain side of a selected memory cell; and the other is applied to unselected memory cells located on the source side of a selected memory cell.